• LCMXO2-7000HC-4TG144C 144TQFP FPGA IC 114 I/O Integrated Circuits
LCMXO2-7000HC-4TG144C 144TQFP FPGA IC 114 I/O Integrated Circuits

LCMXO2-7000HC-4TG144C 144TQFP FPGA IC 114 I/O Integrated Circuits

Product Details:

Place of Origin: original
Brand Name: original
Certification: original
Model Number: LCMXO2-7000HC-4TG144C

Payment & Shipping Terms:

Minimum Order Quantity: 1
Price: negotiation
Packaging Details: carton box
Delivery Time: 1-3working days
Payment Terms: T/T, L/C
Supply Ability: 100,000
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Detail Information

Package: Tray Product Status: Active
Digi-Key Programmable: Not Verified Number Of LABs/CLBs: 858
Number Of Logic Elements/Cells: 6864 Total RAM Bits: 245760
Number Of I/O: 114 Voltage - Supply: 2.375V ~ 3.465V
High Light:

LCMXO2-7000HC-4TG144C

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144TQFP FPGA IC

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144TQFP FPGA Integrated Circuits

Product Description

LCMXO2-7000HC-4TG144C General Purpose Relays Ic Fpga 114 I/O 144tqfp
 

MachXO2 Field Programmable Gate Array (FPGA) IC 114 245760 6864 144-LQFP

 

Specifications of  LCMXO2-7000HC-4TG144C

 

TYPE DESCRIPTION
Category Integrated Circuits (ICs)
Embedded
FPGAs (Field Programmable Gate Array)
Mfr Lattice Semiconductor Corporation
Series MachXO2
Package Tray
Product Status Active
Digi-Key Programmable Not Verified
Number of LABs/CLBs 858
Number of Logic Elements/Cells 6864
Total RAM Bits 245760
Number of I/O 114
Voltage - Supply 2.375V ~ 3.465V
Mounting Type Surface Mount
Operating Temperature 0°C ~ 85°C (TJ)
Package / Case 144-LQFP
Supplier Device Package 144-TQFP (20x20)
Base Product Number LCMXO2-7000

 

Features of LCMXO2-7000HC-4TG144C

 

 Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and18 to 334 I/Os

 Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 22 µW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

 Embedded and Distributed Memory

• Up to 240 kbits sysMEM™ Embedded BlockRAM

• Up to 54 kbits Distributed RAM

• Dedicated FIFO control logic

 On-Chip User Flash Memory

• Up to 256 kbits of User Flash Memory

• 100,000 write cycles

• Accessible through WISHBONE, SPI, I2C andJTAG interfaces

• Can be used as soft processor PROM or asFlash memory

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• 7:1 Gearing for Display I/Os

• Generic DDR, DDRX2, DDRX4

• Dedicated DDR/DDR2/LPDDR memory withDQS support

 High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports widerange of interfaces:

– LVCMOS 3.3/2.5/1.8/1.5/1.2

– LVTTL

– PCI

– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

– SSTL 25/18

– HSTL 18

– Schmitt trigger inputs, up to 0.5 V hysteresis

• I/Os support hot socketing

• On-chip differential termination

• Programmable pull-up or pull-down mode

 Flexible On-Chip Clocking

• Eight primary clocks

• Up to two edge clocks for high-speed I/Ointerfaces (top and bottom sides only)

• Up to two analog PLLs per device withfractional-n frequency synthesis

– Wide input frequency range (7 MHz to400 MHz)

 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single-chip, secure solution

• Programmable through JTAG, SPI or I2C

• Supports background programming of non-volatile memory

• Optional dual boot with external SPI memory

TransFR™ Reconfiguration

• In-field logic update while system operates

 Enhanced System Level Support

• On-chip hardened functions: SPI, I2C, timer/counter

• On-chip oscillator with 5.5% accuracy

• Unique TraceID for system tracking

• One Time Programmable (OTP) mode

• Single power supply with extended operatingrange

• IEEE Standard 1149.1 boundary scan

• IEEE 1532 compliant in-system programming

 Broad Range of Package Options

• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,fpBGA, QFN package options

• Small footprint package options

– As small as 2.5 mm x 2.5 mm

• Density migration supported

• Advanced halogen-free packaging

 

Architecture Overview of LCMXO2-7000HC-4TG144C
 
The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2-1 and Figure 2-2 show the block diagrams of the various family members.
 

Environmental & Export Classifications of LCMXO2-7000HC-4TG144C

 

ATTRIBUTE DESCRIPTION
RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 3 (168 Hours)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001
 
LCMXO2-7000HC-4TG144C 144TQFP FPGA IC 114 I/O Integrated Circuits 0

 

 

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